To provide state-of-the-art digital circuit design consulting for advanced semiconductors specializing in custom and semi-custom memory systems.

The cornerstone of our service is built on a wholistic approach that leverages methodology, testability and innovation to ensure a robust high yielding part.

We implement low-energy, high-performance design styles while minimizing risk.

Vision Statement

LEARN ABOUT OUR SERVICES

"Every Femto Farad, Femto Joule and Femto Amp Counts"

CURRICULUM VITAE

CUSTOM CIRCUIT DESIGN

In a competitive, high-tech marketplace, there are occasions when a synthesized solution is not going to make it.

This is where a custom circuit designer can step in and tweak out the last femto second/farad/joule and optimize your silicon!

METHODOLOGY & CAD SUPPORT

Methodology and CAD tools have become indispensable and complement each other.

Implementing sound methods and applying CAD tools can help ensure working first silicon.

You need an "Expert User" to run these tools and interpret results.

1979 ~ 2000

PowerPC 64-bit Microprocessor (1.3V, 0.13um, SOI, 9-layer copper)
- 4-way set associative TLB array for 2 GHz operation
PowerPC 7400/7450 with AltiVec (1.8V, 0.20um CMOS, 6-layer copper)
- 32KB embedded Data Cache with Castout/Reload
PowerPC 604e Microprocessor (1.8V, 0.25um CMOS, 6-layer aluminum)
- 32KB embedded Data Cache with improved noise margin for 350MHz
68EC/LC060 Microprocessor (0.5um, CMOS, 3-layer metal interconnect)
- Project Lead for re-floorplaned and low-cost version of 68060
68060 Microprocessor (0.5um CMOS, 3-layer metal interconnect)
VAX 9000 Vector Register File for digital equipment mainframe (High Speed Bipolar Mosaic-3)
- 1Kx9 Self-Timed register file for use in vector processor
MiPS R3000A Multi-Chip Module signal integrity analysis
Wafer Scale Integration Test Vehicle (E2SAT, 6-layer, 1um Bipolar Process)
IBM 4381 Mainframe Core Memory (1Kx9 SRAM with CTS bit cell, 3um Bipolar process)
NMOS Custom Logic Test Chip (Double poly, 2.5um depletion Nmos process)

2001 ~ 2018

Apple Processor Embedded Custom Cells
- Essentially worked on every generation from A4 --> A12 Bionic Processor and beyond.
  - These were very complex designs with large teams
  - Process technology was state-of-the-art
  - My focus was the design/analysis/verification of specific custom megacells for integration into the SOC

Intrinsity Custom Chip for Agere Processor (FAST14)
Intrinsity Cortex-A8 Processor (Samsung 45nm process)
- Special purpose dual port arrays

Atom Processor for Silverthorne Platform (45nm CMOS)
- Multi-Core for up to 8 "tiny" cores for Low Power
- 1st Level Instruction Cache Register File

Tejas Pentium-4 Processor (1.3V, 90nm, 5Ghz)
- 32KB 2nd Level Tag for 4MB 2nd Level Cache

1979 ~ 1984

1985~ 1991

1992 ~2000

2001 ~ 2006

E

APPL

2007 ~ 2018

PATENTS

PAPERS

Motorola encouraged papers to be written for conferences and journals

Steve taught memory design classes at the University of Texas (Austin) as a "Guest Lecturer" for a VLSI Master's degree program

"The Superscalar Architecture of the MC68060"
- IEEE MICRO , APRIL 1995

"A 450MHz PowerPC Microprocessor With Enhanced Instruction SetAnd Copper Interconnect"
- 1999 IEEE International Solid State Circuits Conference

"A 1.8V , 2.0ns Cycle , 32KB Embedded Memory With Interleqved Castout/Reload"
- IEEE 1999 Custom Integrated Circuits Conference

"A 450-MHz RISC Microprocessor With Enhanced Instruction SetAnd Copper Interconnect"
- IEEE Journal of Solid State Circuits, Nov 1999

LaVoy & Chernoff, P.C.

Tiffany & Bosco, P.A.

I have performed "Expert Witness" discovery for Chris LaVoy and Mike Chernoff in support of a patent litigation case in 2006. The patent infringement suit was related to reconfigurable word-width memory design against a leading FPGA manufacturer resulting in a multi-million dollar settlement.