Part-1
Bitcell Comparison
"Comparison Between Two Bipolar Bitcells"
This is an informal tutorial about how an actual SRAM design might be done in practice using a classic solid-state technology; Bipolar. My first exposure to bipolar technology was around 1980 when bipolar was the standard method of high-speed silicon implementation in static memory for mainframe computers during the 1970's and 1980's.
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A static memory chip known as an SRAM (Static Random Access Memory) maintains state while being "powered-up", but is volatile in that it loses storage if the power is removed or "powered-down". This concept helped to simplify the design back then because you assumed that power was "always ON" and loss of supply (VCC for bipolar, VDD for CMOS) would indicate that the system was re-booting or shutting down (loss of data was a don't-care). However, later I found that in CMOS one could make use of several voltage levels that could reduce leakage currents while maintaining state. (These states can be called something like "SLEEP MODE"and adds complexity in timing and requires prevention of latch-up issues to be discussed later).
In this tutorial, we will be comparing two different bitcells. Personally, I've always wanted to do this sort of comparison back around 1984 when I joined a start-up company that used a different bitcell because I wondered which one was "the better choice". What were the trade-offs between the two bitcell types? (as you will see, they are quite different!) Why would someone choose one over the other? Is there a big difference in the amount of area and power that one type consumed over the other? Was one bitcell type more stable than the other? Was it more difficult to achieve speed/performance goals for the product to be successful and delivered "on-time"? Another subtle question might be; is one of them more difficult to verify using CAD tools (i.e., layout, DRC, ERC, logical, functional, power-sequencing, soft-error rate, etc) This is a deceptively complex question that is difficult to evaluate. However, I quickly learned that an engineer does not want to spend several days/weeks in a lab doing silicon debug analysis! (NOTE: Start-up companies usually don't have time to do much research and "what-if" scenarios; they need a product out-the-door).
Figure-1) ECL bit cell with parallel schottky diodes
Figure-2) CTS bitcell with schottky access diodes
The intent is to compare the two bit cell types with as much common peripheral circuitry as possible (for an "apples-to-apples" comparison). So, I will attempt to utilize shared circuits such as address decoders, sense amplifiers and word line drivers, etc. in order to create a common circuit environment.
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In the final analysis, hopefully area and power components of the peripheral circuits can be factored-out and the impact of using one cell type over the other would become more obvious.