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Tejas was a Pentium-4 class microprocessor targeting greater than 4Ghz clock speed using 90nm technology.
Also, a very intense experience since schedule was dominating the project.
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My focus was the TAG array for the L2 Cache (roughly the top third of the die) It was a highly pipelined architecture to achieve cycle time.
Is should be noted that after Tejas was completed, I had the good fortune of working on a new concept processor. The idea was to create many small processors that were activated based on the processor load, thereby saving significant power. The project turned into the ATOM processor for highly mobile devices.
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